1. Field of the Invention
The present invention relates to a CMOS image sensor and a method for manufacturing the same. More particularly, the present invention relates to a CMOS image sensor and a method for manufacturing the same that improves photosensitivity and obtains high integration by forming a photo-sensing unit under a color filter.
2. Discussion of the Related Art
An image sensor is a semiconductor device for converting an optical image to an electric signal. The image sensor is classified into charge coupled devices (CCD) and complementary metal oxide silicon (CMOS) image sensors.
In a CCD, metal-oxide-silicon (MOS) capacitors are adjacently arranged, and electric carriers are stored in and transferred from the MOS capacitors. In a CMOS image sensor, the number of MOS transistors corresponds to the number of pixels. This is enabled by CMOS technology of using a control circuit and a signal processing circuit as peripheral circuits, whereby output signals are sequentially outputted with the MOS transistors in a switching method.
The CMOS image sensor changes information of objects to electric signals. The CMOS image sensor includes signal processing chips which include photodiodes. Each of the signal processing chips is provided with an amplifier, an analog-digital converter, an internal voltage generator, a timing generator, and a digital logic. The CMOS image sensor has advantages in that it can realize the decrease in space, power and cost.
Also, the CCD is manufactured by a high-priced specialized process. However, the CMOS image sensor is manufactured in a mass production by an inexpensive silicon wafer etching process. In addition, the CMOS image sensor has high integration.
Generally, the CMOS image sensor includes a photo-sensing unit and a logic circuit unit, wherein the photo-sensing unit receives the light, and the logic circuit unit converts the light to electric signals. In order to improve photosensitivity, there is a requirement for increasing an occupying area of the photo-sensing unit in the entire CMOS image sensor. However, since an entire area of the CMOS image sensor is fixed, the aforementioned method for increasing the occupying area of the photo-sensing unit has limits. Accordingly, there is a requirement for condensing the light so that it may reach the photo-sensing unit by changing the path of light incident on the remaining areas except the photo-sensing unit. For this, a micro-lens is provided to correspond to the photo-sensing unit on a color filter array.
The color filter array may be formed of red, green and blue colors, or may be formed of yellow, magenta and cyan colors.
A CMOS image sensor according to the related art will be described with reference to the accompanying drawings.
FIGS. 1A to 1F are cross sectional views illustrating a method for manufacturing a CMOS image sensor according to the related art.
As shown in FIG. 1A, P-type ions, such as boron ions, are selectively implanted to a semiconductor substrate 100, thereby forming a P-type well 101. For device isolation, a predetermined portion of the semiconductor substrate 100 is selectively etched, and is then filled with an insulating layer, thereby forming a field oxide layer 102.
Then, a gate oxide layer (not shown) is formed on the semiconductor substrate 100. Also, a gate electrode 105 is formed on the gate oxide layer, wherein the gate electrode 105 is comprised of a polysilicon layer 103 and a tungsten silicide layer 104.
Subsequently, lightly-doped N-type and P-type diffusion regions 106 and 107 are formed in a photo-sensing area of the semiconductor substrate 100. As a result, a photodiode is formed in the photo-sensing area of the semiconductor substrate 100.
For obtaining an LDD (Lightly Doped Drain) structure in source and drain regions of a transistor, lightly-doped N-type LDD regions 108 are formed in the semiconductor substrate 100 to correspond to both sides of the gate electrode 105. Then, a TEOS oxide layer (not shown), or a nitride layer (not shown), is deposited by LPCVD. The TEOS oxide layer is then anisotropically etched, to form spacers at both sidewalls of the gate electrode 105. Also, a highly-doped N-type diffusion region 110 is formed in the surface of the semiconductor substrate 100.
Referring to FIG. 1B, the TEOS oxide layer, or nitride layer, is deposited at a thickness of about 1000 Å by LPCVD. Also, a BPSG layer (not shown) is formed on the TEOS oxide layer by HPCVD.
Then, a first metal dielectric layer 111 is formed by flowing the BPSG layer. Also, a contact hole 112 for exposing the highly-doped N-type diffusion region 110 is formed by selectively etching the first metal dielectric layer 111. After forming a first glue layer 113 of titanium Ti, a first aluminum layer 114 for line formation is formed on the first glue layer 113. Then, a first titanium nitride layer 115 of the non-reflective property is formed on the first aluminum layer 114. Then, the first glue layer 113, the first aluminum layer 114 and the first titanium nitride layer 115 are selectively etched to form a first metal line 116. The contact hole 112 is formed in a plasma etching process.
Referring to FIG. 1C, a TEOS oxide layer 117 is formed by PECVD (Plasma Enhanced Chemical Vapor Deposition). Also, an SOG (Spin On Glass) oxide layer 118 is coated on the TEOS oxide layer 117, and then a heat treatment and a planarization process are applied thereto.
Then, a first PECVD oxide layer 119 is formed on the first TEOS oxide layer 117 and the first SOG oxide layer 118. The first TEOS oxide layer 117, the first SOG oxide layer 118 and the first PECVD oxide layer 119 constitute a second metal dielectric layer.
As shown in FIG. 1D, a via-hole 121 is formed by selectively etching the second metal dielectric layer. Then, after forming a second glue layer 122 of titanium Ti, a second aluminum layer 123 is formed on the second glue layer 122. A second titanium nitride layer 124 having a non-reflective property is formed on the second aluminum layer 123. Then, the second glue layer 122, the second aluminum layer 123 and the second titanium nitride layer 124 are selectively etched by plasma, thereby forming a second metal line 125.
Subsequently, a second TEOS oxide layer 126 is formed on an entire surface of the semiconductor substrate including the second metal line 125. Then, a second SOG oxide layer 127 is formed on the second TEOS oxide layer 126, and a second PECVD oxide layer 128 is formed on the second SOG oxide layer 127.
The second TEOS oxide layer 126, the second SOG oxide layer 127 and the second PECVD oxide layer 128 constitute a third metal dielectric layer. By repeating the above-mentioned steps, it is possible to form metal lines.
As shown in FIG. 1E, an oxide layer is formed at a thickness of about 8000 Å on the third metal dielectric layer by PECVD. The oxide layer functions as a passivation layer 129. Then, the passivation layer 129 and the third metal dielectric layer, which correspond to a peripheral circuit area, are selectively etched to form a pad opening area 130 for an electrode terminal.
As shown in FIG. 1F, a color filter array 131 and a planarization layer 132 are sequentially formed on the passivation layer 129. Then, a micro-lens 133 is formed on the planarization layer 132.
FIG. 2 is a layout of a photo-sensing unit and a gate operating unit in the CMOS image sensor according to the related art. As shown in FIG. 2, the photo-sensing unit 134 is separately formed from the gate operating unit 135.
However, the related art CMOS image sensor and the method for manufacturing the same have the following disadvantages.
First, because the photo-sensing unit is separately formed from the color filter array, a loss of light occurs. Since a thick dielectric material is formed between the photo-sensing unit and the color filter array, the amount of incident light that reaches the photodiode is decreased due to absorption, refraction and reflection of light. Thus the photosensitivity of the CMOS image sensor is lowered. In addition, since the photo-sensing unit and the gate operating unit are separately formed from each other, it is difficult to realize high-integration of the CMOS image sensor.